1. Field of the Invention
The present invention relates in general to a memory management system and more particularly, to a memory management system for managing pointers in a network.
2. Description of the Prior Art
The need for faster communication among computers and other systems requires ever faster and more efficient networks. Today, networks typically use an amalgam of various software and hardware to implement a variety of network functions and standards. Network devices such as client computer systems, servers, hubs, routers, switches, network backbones, etc., are each complex devices that require digital processing in hardware and software to facilitate network communication. Some tasks performed in a network device include translation between different network standards such as Ethernet and ATM, reformatting data, traffic scheduling, routing data cells, packets messages, etc. Depending on the particular protocol being implemented, some tasks may be performed at different points in the network.
In conventional networking systems that implement ATM, data traffic is handled by a Virtual Channel, or Virtual Connection (VC). There are typically many VCs in each system and each VC has its own characteristics, such as packet type, packet size and protocols. For each VC, a descriptor which identifies the particular VC and its characteristics and requirements is stored in a memory. When a scheduler determines that a particular VC is ready for transmission, the VC descriptor is accessed and processed to determine the appropriate characteristics and requirements for cell transmission on the particular connection.
Pointers are generally used within these networking systems for accessing the memory. In order to improve overall performance and speed of the systems, efficient management dictates that available pointers be located as quickly as possible.
A system for managing a pointer system that includes a plurality of pointers in accordance with the present invention includes at least one memory device wherein each pointer is assigned an address in the memory device and each address has a first value when its corresponding pointer is not in use and a second value when its corresponding pointer is in use. The system further includes logic for combining the values into a first group of values wherein each of the first group of values is assigned to an address in the memory device. Additionally, the system includes logic for combining the first group of values into a second group of values wherein each of the second group of values is assigned to an address in the memory device.
In accordance with a method of managing a pointer system in accordance with the present invention, a memory address for each pointer is assigned and a value is assigned to each memory address based upon whether or not the corresponding pointer is occupied or not. In one preferred embodiment, the value assigned to the memory address if the corresponding pointer is occupied is a logic 0. The values assigned to each memory address are then ORed, preferably within rows of the memory device. Thus, each row would then have a value based upon the ORing function. Each row value is then entered into an address location within the memory device. These first group of values are then also ORed. In a preferred embodiment, the ORing is within rows of the memory device to arrive at a second group of values, which may be referred to as areas. This second group of values or area values are then entered either into memory locations within the memory device or, in a preferred embodiment, into flip-flops.
Thus, in order to efficiently find an available pointer, the area values are evaluated until a logic 1 is located thus indicating that at least one of the rows within that particular area includes a logic 1. The corresponding area is then searched until a row is located whose memory address has a logic 1 value, thus indicating that one of the pointer addresses within that row has a logic 1 value. The corresponding row is then searched until a memory address having a logic 1 is located indicating that that particular pointer is available.
Reference to the remaining portions of the specification, including the drawings and claims, will realize other features and advantages of the present invention. Further features and advantages of the present invention, as well as the structure and operation of various embodiments of the present invention, are described in detail below with respect to the accompanying drawings. In the drawings, like reference numbers indicate identical or functionally similar elements.